Technical Field
The disclosure relates to a semiconductor structure and a manufacturing method for the same, and more particularly to a MOS and a manufacturing method for the same.
Description of the Related Art
For forming a designed integrated circuit to a semiconductor wafer, a mask formed with a design layout pattern is provided. The layout pattern defined by the photomask is transferred on to a photoresist layer on a surface of a semiconductor structure and then transferred into the semiconductor structure by photolithography processes. Therefore, the photolithography process is an important key for the semiconductor manufacturing.
The critical dimension (CD) of the pattern for the photomask is limited to the resolution limit of the optical exposure tool. With the trend towards high integration and small pattern of the circuit design, the deviation or the distortion of the pattern transferred into the semiconductor structure occur more easily due to the optical proximity effect (OPE) during exposing the photomask having high pattern density. The electrical characteristic of the device is affected by the distortion.